The invention relates generally to the storage of data in a high speed computer environment, and in particular to a buffer allocation circuit for directing input data packets to avaiable buffer memories for later access by a host computer.
In a data communications environment, if often occurs that incoming data packets must be directed in real time and under severe time constraints into one of a plurality of available buffers. In those environments where the data flow cannot be interrupted, for example a high speed computer network, rapid assessment of which buffers are already written with data, and hence are unavailable, must be made. The data must be directed therefore to those buffers which are empty, or which had been written and subsequently emptied or processed, to avoid data loss.
When the data is incoming at extremely high data rates, and is not interuptable, the circuitry to direct the data has been expensive and complex. Further, as the number of buffer memories increases, the directing circuitry generally increased according to the square of the number of buffers employed. As a result, systems with large numbers of buffer memories require very complex direction circuitry; and this very same complex direction circuitry thus tends to inhibit the use of additional memories which would otherwise expand the memory capabilities of the apparatus.
It is therefore an object of this invention to reliably direct incoming, uncontrolled and uninterruptable data, to available buffer memories without loss of data and with minimum circuit complexity. Further objects of the invention are circuitry that can be linearly expanded to service additional buffer memories in a simple and reliable manner, and circuitry that can be expanded at minimum cost consistent with reliable and error free data reception.